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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 11862,278
- Publication Date: January 02, 2024
- Appl. No: 17/433354
- Application Filed: March 12, 2021
- Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC. (Hefei, CN)
- Claim: 1. A memory test system, comprising: a plurality of test devices, each of which is provided with a test interface used for connecting a memory to be tested; a host computer, respectively connected to the plurality of test devices and configured to control the plurality of test devices to test the memory to be tested; and driving modules, connected to the plurality of test devices and configured to output, to the plurality of test devices, driving signals used for driving the plurality of test devices to perform data interaction with the host computer; wherein the driving modules comprise: first driving units, configured to transmit, to the plurality of test devices, first driving signals used for driving the plurality of test devices to perform data interaction with the host computer; and test units, configured to store test programs; and the host computer comprises: a second driving unit, by which the host computer is connected to the plurality of test devices, the second driving unit being configured to transmit, in response to the first driving signals, a second driving signal to the plurality of test devices to realize the data interaction between the plurality of test devices and the host computer.
- Claim: 2. The memory test system according to claim 1 , wherein the memory test system comprises a plurality of driving modules and each of the plurality of test devices is connected to one of the plurality of driving modules.
- Claim: 3. The memory test system according to claim 1 , wherein the host computer and the plurality of test devices are connected by wired connection or wireless connection.
- Claim: 4. The memory test system according to claim 1 , wherein the plurality of test devices are Unified Extensible Firmware Interface based (UEFI-based) memory verification platforms; and the plurality of test devices further comprise: storage units, configured to store test results of the memory to be tested.
- Claim: 5. A memory test method, comprising: transmitting a test request used for requesting connection to a host computer; receiving a test instruction which is a signal transmitted by the host computer according to the test request; determining, based on the test instruction, whether a driving module has a first preset test strategy; testing memory to be tested by the first preset test strategy to obtain a first test result, when the driving module has the first preset test strategy; and obtaining a first initial test strategy from the host computer, and testing the memory to be tested by the first initial test strategy to obtain a first test result, when the driving module does not have the first preset test strategy.
- Claim: 6. The memory test method according to claim 5 , further comprising: transmitting the first test result to the host computer, the host computer being configured to determine, according to the first test result, whether to test the memory to be tested by a second test strategy; and receiving the second test strategy and testing the memory to be tested by the second test strategy to obtain a second test result, when it is determined to test the memory to be tested by the second test strategy.
- Claim: 7. The memory test method according to claim 5 , further comprising: storing the first test result in a storage unit.
- Claim: 8. The memory test method according to claim 5 , further comprising: connecting the host computer by using the driving module to realize data interaction with the host computer.
- Claim: 9. The memory test method according to claim 8 , further comprising: loading a test program from the driving module to test the memory to be tested by the test program.
- Claim: 10. The memory test method according to claim 5 , wherein the first preset test strategy is any one or more of chessboard algorithm, 0/1 read and write test, marching algorithm, galloping algorithm, or butterfly algorithm.
- Claim: 11. A memory test method, comprising: receiving a test request which is transmitted by a test device; transmitting a test instruction to the test device according to the test request; and upon receiving a test strategy request, transmitting a first initial test strategy to the test device, the first initial test strategy being used for testing memory to be tested; wherein the test strategy request is a request transmitted by the test device, when a driving module does not have a first preset test strategy.
- Claim: 12. The memory test method according to claim 11 , further comprising: receiving a first test result, the first test result being a result obtained by testing, by the test device, the memory to be tested by the first preset test strategy or the first initial test strategy; determining, according to the first test result, whether to test the memory to be tested by a second test strategy; and transmitting a second test strategy to the test device when it is determined to test the memory to be tested by the second test strategy, the second test strategy being used for testing the memory to be tested.
- Claim: 13. The memory test method according to claim 12 , further comprising: transmitting a test end instruction to the test device, when it is determined not to test the memory to be tested by the second test strategy.
- Claim: 14. The memory test method according to claim 11 , wherein the first preset test strategy is any one or more of chessboard algorithm, 0/1 read and write test, marching algorithm, galloping algorithm, or butterfly algorithm.
- Patent References Cited: 6324666 November 2001 Nakamoto ; 6477672 November 2002 Satoh ; 7009380 March 2006 Chen ; 7707473 April 2010 LaBerge ; 8001434 August 2011 Lee ; 8095841 January 2012 Kemmerling ; 20040019839 January 2004 Krech, Jr. ; 20050010842 January 2005 Burke, Jr. ; 20080082889 April 2008 Agata ; 20110000829 January 2011 Linde ; 20140053032 February 2014 Ho ; 20140068360 March 2014 Lai et al. ; 20150038109 February 2015 Salahshour ; 20150100824 April 2015 Lucas ; 20150213291 July 2015 Gut ; 20160086678 March 2016 Botea ; 106201803 December 2016 ; 108107867 June 2018
- Other References: International Search Report cited in PCT/CN2021/080448 dated Jun. 10, 2021, 10 pages. cited by applicant
- Primary Examiner: Pham, Ly D
- Attorney, Agent or Firm: Cooper Legal Group, LLC
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